In a device for read and write of data on a storage medium such as a CD-R, a CD-RW or a DVD-RAM, a laser diode and a laser diode drive circuit are used to irradiate the storage medium with light for read or write of data.
Ordinarily, a laser diode drive circuit is, as shown in FIG. 19, constituted by an oscillator 1, a high-speed current switch circuit (or high-frequency current source) 2, and a high-speed current switch circuit 3.
The high-speed current switch circuit (high-frequency current source) 2 is arranged to switch a current flowing through a laser diode 4 on the basis of an oscillating output from the oscillator 1. The high-speed current switch circuit 2 forms a high-frequency superimposition circuit. The high-speed current switch circuit 3 is arranged to switch a current flowing through a laser diode 4 on the basis of a signal externally supplied.
As this kind of laser diode drive circuit, a high-speed current switch circuit is demanded in which a large current for driving a laser diode is caused to rise at a high rate, and in which the overshoot of the current when the current rises is limited.
For example, a circuit shown in FIG. 20 is known as a conventional high-speed current switch circuit.
This conventional high-speed current switch circuit has an output MOS transistor Q1, a switch SW1 connected to the drain of the MOS transistor Q1, a MOS transistor Q2 which supplies a predetermined bias voltage to the MOS transistor Q1, and a constant current source I1 which supplies a constant current to the MOS transistor Q2.
As shown in FIG. 21, the switch SW1 is constituted by a switching MOS transistor Q3. A switching signal is applied to the gate of the MOS transistor Q3 through a buffer BF.
In the conventional circuit thus formed, a current flowing through the MOS transistor Q1 is switched by performing open/close control of the switch SW1.
Since in this conventional circuit the switch SW1 is inserted in the current path of the MOS transistor Q1 as shown in FIG. 20, a voltage drop occurs due to the on resistance of the switch SW1. To secure an output compliance range of the circuit, therefore, it is necessary to reduce the on resistance of the switch SW1.
To do so, the size of the MOS transistor Q3 used as switch SW1 as shown in FIG. 21, i.e., the ratio (W/L) of the channel width (W) and the channel length (L), must be increased, resulting in an increase in the gate capacitance Cg of the MOS transistor Q3.
Thus, this conventional circuit has the drawback of having difficulty in performing high-speed switching of the switch SW1. It also has a drawback in that when an output current rises, charge injection through the switch SW1 can easily cause a considerably large overshoot.
Another conventional high-speed current switch circuit shown in FIG. 22 is known.
This another conventional high-speed current switch circuit has an output MOS transistor Q1, a MOS transistor Q2 which supplies a predetermined bias voltage to the MOS transistor Q1, and a constant current source I1 which supplies a constant current to the MOS transistor Q2. The gate of the MOS transistor Q1 and the gate of the MOS transistor Q2 are connected to each other through a switch SW2, and the gate of the MOS transistor Q1 is grounded through a switch SW3.
In this another conventional circuit thus arranged, a voltage applied to the gate of the MOS transistor Q1 is controlled by alternately closing the switch SW2 and the switch SW3 to switch a current Iout drawn by the MOS transistor Q1.
That is, the gate voltage on the MOS transistor Q1 is set to a bias supply voltage Vb supplied from the MOS transistor Q2 by setting the switches SW2 and SW3 in the closed state and in the open state, respectively, to turn on the MOS transistor Q1. Alternatively, the gate voltage on the MOS transistor Q1 is set to ground potential Vss by changing the states of the switches SW2 and SW3 so that the switches SW2 and SW3 are set in the open state and in the closed state, respectively, to turn off the MOS transistor Q1.
In this another conventional circuit, a rise time τ during which the gate voltage on the MOS transistor Q1 rises from the ground potential Vss to the bias supply voltage Vb is determined by the following equation (1):τ=R×Cg  (1)where R is the sum of the on resistance Ron of the switch SW2 and the value of 1/Gm of the transistor Q2, and Cg is the gate capacitance of the MOS transistor Q1.
This shows that reducing the on resistance Ron of the switch SW2 or reducing the value of 1/Gm of the transistor Q2 are necessary for enabling high-speed current switching.
To reduce the on resistance of the switch SW2, the size of the MOS transistor Q3 used as switch SW2 as shown in FIG. 21, i.e., the ratio (W/L) of the channel width (W) and the channel length (L), must be increased, resulting in an increase in the gate capacitance Cg of the MOS transistor Q3.
Thus, another conventional circuit also has the drawback of having difficulty in performing high-speed switching of the switch SW2. It also has a drawback in that when an output current rises, a considerably large overshoot can occur easily because charge injection through the switch SW2 occurs on the gate of the transistor Q1.
To reduce 1/Gm of the MOS transistor Q2, it is necessary to increase the current I1 flowing through the MOS transistor Q2 or the size of the MOS transistor Q2, i.e., the value of W/L. Increasing the current I1, however, entails a drawback in that the consumption current in the circuit is increased.
Increasing the size of the MOS transistor Q2, i.e., the value of W/L, involves increasing the size of the MOS transistor Q1 if the output current is constantly maintained, because the MOS transistor Q1 and the MOS transistor Q2 are in the current-mirror relationship. An increase in the gate capacitance of the MOS transistor Q1 also results. Thus, there is a drawback in that the circuit area is increased while the effect of increasing the switching speed is not sufficiently high.
If there is a need to cause a large current to flow through the MOS transistor Q1, the transistor size (W/L) of the MOS transistor Q1 must be increased, resulting in an increase in the gate capacitance Cg of the MOS transistor Q1. An increase in rise time τ results. Thus, this another conventional circuit also has the drawback of having difficulty in performing high-speed switching of the MOS transistor Q1.
In the oscillator used in this kind of laser diode drive circuit, the frequency of unwanted emission noise from the circuit is determined by the oscillation frequency of the oscillator since the oscillation output from the oscillator is used for control of the high-speed current switch circuit. Therefore, an oscillator in which variation in oscillation frequency is limited and in which the oscillation frequency is not easily changed by a change in temperature or power supply voltage during operation is required by considering the facility with which means is adopted to cope with unwanted emission noise.
For example, a ring oscillator such as shown in FIG. 23 is known as a conventional oscillator corresponding to that shown in FIG. 19.
In this ring oscillator, inverters (inverting devices) 4, e.g., CMOS inverters are connected in series in an odd number of stages as shown in FIG. 23 and an output from the final stage is fed back to the input to the initial stage to perform self-excited oscillation.
The oscillation frequency f of such a ring oscillator is expressed by the following equation (2):f=½nτ  (2)where n is the number of stages in which inverters 4 are connected and τ is a delay time per inverter 4 stage.
The oscillator arranged as described above has a drawback in that the operating speed of the inverter 4 changes due to a change in operating temperature, a change in power supply voltage, a difference between manufacturing process conditions, or the like, and the oscillation frequency can easily vary largely.
An oscillator shown FIG. 24 is known as one designed so as to be improved in terms of variation in oscillation frequency. That is, this oscillator is designed to reduce variation in oscillation frequency by providing a current limiter for each of inverters 5, the limiter limiting a current i supplied to inverters 5. The current value i of the current limiter may be made variable to enable the oscillation frequency to be changed.
This oscillator, however, also has a drawback in that the oscillation frequency varies due to changes in power supply voltage or variation in the capacitance value of capacitive elements Cm. There is also a problem that the oscillation frequency varies, as is that in the oscillator shown in FIG. 23, if the value of the limit current of the current limiter is large.
In view of the above-described problems, a first object of the present invention is to provide a high-speed current switch circuit capable of operating at a high speed.
A second object of the present invention is to provide a high-frequency current source arranged to produce a high-frequency current by being combined with the above-mentioned high-speed current switch circuit.
A third object of the present invention is to provide a high-speed current switch circuit capable of operating at a high speed without increasing consumption current.
A fourth object of the present invention is to provide a high-speed current switch circuit in which the overshoot when an output current rises is reduced, and which is capable of operating at a high speed.
A fifth object of the present invention is to provide an oscillator designed so as to stabilize the oscillation frequency as well as to improve the oscillation accuracy.
A sixth object of the present invention is to provide a high-frequency superimposition circuit which operates at a high speed with stability.